Very low power logic circuit family with enhanced noise immunity

Details Very low power logic circuit family with enhanced noise immunity Very low power logic circuit family with enhanced noise immunity

1998-10-15

2000-08-29

Tokar, Michael

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326 23, 326 83, H03K 1716

Patent

active

061114251

ABSTRACT:
A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.

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IBM Technical Disclosure Bulletin, vol. 32, No. 1, Jun. 1989, "NMOS Control Circuit For A CMOS Three-State Driver".

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