Sense amplifier circuit coupled to a bit line pair for increasin

Details Sense amplifier circuit coupled to a bit line pair for increasin Sense amplifier circuit coupled to a bit line pair for increasin

1990-08-13

1991-07-02

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Differential sensing

365185, 365190, 365207, 365210, G11C 702

Patent

active

050291386

ABSTRACT:
A sense amplifier circuit is associated with at least one memory cell and comprises a series combination of a first p-channel type transistor and a second n-channel type transistor coupled between a source of positive voltage level and a first input node, a first negative feedback loop coupled between the first input node and the second n-channel type transistor, a series combination of a third p-channel type transistor and a fourth n-channel type transistor coupled between the source of positive voltage level and a second input node, a second negative feedback loop coupled between the second input node and the fourth n-channel type transistor, an output circuit coupled to the first and third n-channel type transistors in a current-mirror fashion and producing an output data signal, and first and second load elements respectively coupled between the first and second input nodes and a ground node, wherein each of the first and second load elements is smaller in conductance than the memory cell and restricts the associated input node to excessively fluctuate upon a change of memory cell to be accessed.

REFERENCES:
patent: 4796230 (1989-01-01), Young
patent: 4916665 (1990-04-01), Atsumi et al.
patent: 4949307 (1990-08-01), Campardo
patent: 4951252 (1990-08-01), White et al.
patent: 4958325 (1990-09-01), Nakagome et al.

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