Static information storage and retrieval – Read/write circuit – Testing
Patent
1995-03-29
1996-10-15
Zarabian, Amir
Static information storage and retrieval
Read/write circuit
Testing
365218, 36518905, G11C 700
Patent
active
055661130
ABSTRACT:
A comparator compares data read out by a sensing amplifier with input data, and outputs equality data when both of the data are equal to each other, while the comparator outputs inequality data when both of the data are not equal to each other. When the comparator outputs inequality data for at least one time within a predetermined period decided by a control signal, the latch circuit latches and keeps outputting the inequality data. The latch circuit latches and outputs equality data when the comparator continuously outputs equality data within the period. Within the period decided by the control signal, the determination circuit determines whether or not writing has been completed on the basis of output data of the latch circuit. The re-write signal generator circuit sends a re-write signal to a write circuit when the determination circuit determines that writing is not yet completed.
REFERENCES:
patent: 5335198 (1994-08-01), van Burskik et al.
patent: 5386422 (1995-01-01), Endoh
patent: 5414664 (1995-05-01), Lin
Takeshi Nakayama, et al., "A 60ns 16Mb Flash EEPROM with Program and Erase Sequence Controller", ISSCC91/Session 16/Non-Volatile And Specialty Memory/Paper FA 16.1, 1991 IEEE International Solid-State Circuits Conference, pp. 260-261.
Miyakawa Tadashi
Saito Hidetoshi
Kabushiki Kaisha Toshiba
Zarabian Amir
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