Method and device for erasing non-volatile semiconductor memory

Details Method and device for erasing non-volatile semiconductor memory Method and device for erasing non-volatile semiconductor memory

1997-12-10

1999-01-19

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular biasing

365218, G11C 1604

Patent

active

058620796

ABSTRACT:
Step S1 is carried out to lower, at the beginning of erasing operation, a voltage across a drain of a memory cell below a positive voltage applied to a source for erasing and then step S2 is carried out to open the drain. At the beginning of the erasing operation, step S3 is carried out to apply the positive voltage to the source and then step S3-1 is carried out to apply a negative voltage to a gate. To complete the erasing operation, step S4 is carried out to force the gate to be at the ground level and then the source to be at the ground level.

REFERENCES:
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5485423 (1996-01-01), Tang et al.
patent: 5535158 (1996-07-01), Yamagata
patent: 5615152 (1997-03-01), Bergemont
patent: 5629893 (1997-05-01), Tang et al.
patent: 5703808 (1997-12-01), Makwana et al.

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