Process and device for testing a memory element

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

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Details

714718, 714799, G11C 2900

Patent

active

059919051

ABSTRACT:
A device and a process for testing a memory element are described. A second memory element is connected in parallel to the first memory element. In order to measure the charge status of the first memory element, the second memory element is brought into a predefined first status and the time required by the second memory element to go from the first status to a second status is measured. This time is analyzed in order to test the memory element.

REFERENCES:
patent: 5345392 (1994-09-01), Mito et al.
patent: 5514946 (1996-05-01), Lin et al.

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