Low latency memory read with concurrent pipe lined snoops

Details Low latency memory read with concurrent pipe lined snoops Low latency memory read with concurrent pipe lined snoops

1997-07-02

1999-11-23

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711154, 711168, 711150, 711169, G06F 1200

Patent

active

059918551

ABSTRACT:
A method processes memory transactions in a computer system having a system memory and a cache memory. The method transmits a memory request to the system memory without waiting for the cache memory to be snooped to determine whether the cache memory stores information in an address corresponding to a selected address of the system memory. The method may transmit a snoop request to the cache memory concurrently with or after the memory request is transmitted to the system memory. The method may be implemented using a system controller having a control switch that uses a first pathway for the memory request and a second pathway for the snoop request so that the snoop and memory requests can be transmitted simultaneously.

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