Memory transactions on a low pin count bus

Details Memory transactions on a low pin count bus Memory transactions on a low pin count bus

1997-09-24

1999-11-23

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Intrasystem connection

System configuring

710 10, G06F 1300

Patent

active

059918411

ABSTRACT:
A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

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