Synchronous random access memory

Details Synchronous random access memory Synchronous random access memory

1994-12-12

1996-05-07

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

36518905, 36518907, 36523008, G11C 1300

Patent

active

055153259

ABSTRACT:
An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for externally output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputer, large size calculator, work station and personal computer can be improved.

REFERENCES:
patent: 5124589 (1992-06-01), Shiomi et al.
patent: 5363330 (1994-11-01), Kobayashi
Electric News, Jun. 6, 1994, p. 70.
Computer Design, Mar. 28, 1994, pp. 47-48.

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