Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1998-02-27
1999-11-23
Nguyen, Tan T.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36523002, G11C 800
Patent
active
059912251
ABSTRACT:
A programmable memory address decode array with vertical transistors having single or split control lines is used to select only functional lines in a memory array. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the decoder. The decoder is programmed at memory test to select an output line responsive to the bits received via the address input lines. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar. The control lines are formed together with interconnecting address input lines. The source regions share a common ground while the drain regions are connected to the output lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to represent a logic function, an area of only 2F.sup.2 is needed per bit of logic, where F is the minimum lithographic feature size.
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Forbes Leonard
Noble Wendell P.
Micro)n Technology, Inc.
Nguyen Tan T.
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