Semiconductor memory device with redundancy control circuits

Details Semiconductor memory device with redundancy control circuits Semiconductor memory device with redundancy control circuits

1998-10-29

1999-11-23

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

059912111

ABSTRACT:
A semiconductor memory device has sets of address fuses which are arranged in a plurality of fuse rows in order to provide a larger number of redundant elements. The sets of address fuses are associated with addresses, respectively, and at least one address fuse included in each of the sets of the address fuses is provided in only one of the fuse rows. Address buses are provided such that the number of address lines associated with the sets of the address fuses is less than the number of fuse rows. One of the address lines is located closer to one of the fuse rows which includes associated address fuses than a center line between the one of the fuse rows and another one of the fuse rows which is adjacent to the one of the fuse rows is. The address lines are connected to redundant element control circuits through local lines.

REFERENCES:
patent: 5798974 (1998-08-01), Yamagata

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