Conductor reticulation for improved device planarity

Details Conductor reticulation for improved device planarity Conductor reticulation for improved device planarity

1994-09-30

1997-11-11

Niebling, John

Fishing, trapping, and vermin destroying

437235, 437228, H01L 2144

Patent

active

056863560

ABSTRACT:
A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g., chemical mechanic polishing or etchback, may be reduced or avoided entirely.

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Neves Aus Der Technik, vol. 2, May 1987, Wursburg, DE, page 2 XP002024607 "Verbesserte Planarisierung", whole article.

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