Process for forming LDD CMOS using large-tilt-angle ion implanta

Details Process for forming LDD CMOS using large-tilt-angle ion implanta Process for forming LDD CMOS using large-tilt-angle ion implanta

1996-03-28

1997-11-11

Tsai, Jey

Fishing, trapping, and vermin destroying

437 44, 437 56, 437 57, 437 58, H01L 21265

Patent

active

056863241

ABSTRACT:
A method and resulting integrated circuit device, and in particular a CMOS integrated circuit device, having a fabrication method and structure therefor for an improved lightly doped drain region. The method includes the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectic over each P type well and N type well regions. The method then performs a blanket N type implant step at an angle being about 45.degree. or greater from a perpendicular to the gate electrodes in both the P type and N type well regions. The blanket N type implant forms an LDD region in the P type well region. Sidewall spacers are then formed on edges of the gate electrodes. The method then performs two separate N type implants into the P type well region, each at different angles and dosages to form the N type LDD source/drain region for an NMOS device. The method also performs two separate P type implants into the N type well region, each at different angles and dosages to form the P type LDD source/drain region for a PMOS device. The present LDD fabrication method provides a relatively consistent and easy to fabricate CMOS LDD region, with less masking steps and improved device performance.

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