Burn-in circuit and burn-in test method

Details Burn-in circuit and burn-in test method Burn-in circuit and burn-in test method

1993-08-02

1995-11-14

Beausoliel, Jr., Robert W.

Excavating

371 214, G11C 2900

Patent

active

054673569

ABSTRACT:
A burn-in enable circuit and burn-in test method of a semiconductor memory device are disclosed. A high voltage exceeding the external power voltage by a predetermined amount is applied to at least one of a plurality of pins normally used with a connected semiconductor memory chip to initiate a burn-in test mode. The burn-in test enable circuit senses this high voltage and causes the reset operation of word lines in the chip to become disabled. This allows for a high stress voltage to be applied to all access transistors in the chip simultaneously during a burn-in test for substantially the same amount of time. Therefore, burn-in time is substantially reduced and a reliable burn-in test is obtained.

REFERENCES:
patent: 4771407 (1988-09-01), Takemae et al.
patent: 5051955 (1991-09-01), Tobita
patent: 5077738 (1991-12-01), Larson
patent: 5119337 (1992-06-01), Shimizu et al.
patent: 5185722 (1993-02-01), Ota et al.
patent: 5208777 (1993-06-01), Shibata
patent: 5258954 (1993-11-01), Furuyama
patent: 5276647 (1994-01-01), Matsai et al.

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