MOS device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257653, H01L 2976

Patent

active

059905182

ABSTRACT:
An n.sup.+ drain layer 2 and an n.sup.- layer 1 on n.sup.+ drain layer 2 constitute a substrate for the semiconductor arrangement. A p-type base region 3 is in the surface portion of n.sup.- layer 1. An n.sup.+ source region 6 is formed in the surface portion of p-type base region 3. A p.sup.+ region 5, deeper than n.sup.+ source region 6 and shallower than p-type base region 3, partially overlaps n.sup.+ source region 6 and extends thoroughly into the portion of p-type base region 3 surrounded by n.sup.+ source region 6. A channel portion 7 is in the surface portion of p-type base region 3 extending between n.sup.- layer 1 and n.sup.+ source regions 6. A gate electrode 8 is disposed above channel portion 7 with a gate insulation film 9 interposed therebetween. A source electrode 11 contacts with p.sup.+ region 5 and n.sup.+ source region 6. An inter-layer insulation film 10 on gate electrode 8 insulates source electrode 11 from gate electrode 8. A drain electrode 12 is on the surface of n.sup.+ drain layer 2. A junction face 20 of p-type base region 3 and n.sup.- layer 1 has a finite radius of curvature such that the depth from the surface of p.sup.+ region 5 to junction face 20 is deepest beneath the center of p.sup.+ region 5.

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patent: 5304831 (1994-04-01), Yilmay et al.
patent: 5521410 (1996-05-01), Yamamoto

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