Compare and exchange operation in a processing system

Details Compare and exchange operation in a processing system Compare and exchange operation in a processing system

1997-01-21

1999-03-30

Ellis, Richard L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395376, 395561, 711214, 711220, G06F 1200

Patent

active

058899839

ABSTRACT:
A technique for providing a compare-and-exchange (CMPXCHG) instruction which may be implemented in an instruction set requiring a limited number of source and destination operands for each instruction in the instruction set. In order to utilize an instruction to perform a read-modify-write operation three source and one destination operands are needed to supply the location of various information used in executing the instruction. Instead of providing all four operands with the instruction, the CMPXCHG instruction of the present invention utilizes an implied operation-specific register. This register is implied in the instruction when the CMPXCHG instruction is executed, so that only two source operands are needed with the CMPXCHG instruction.

REFERENCES:
patent: 5668967 (1997-09-01), Olson et al.
patent: 5696939 (1997-12-01), Iacobovici et al.
patent: 5701442 (1997-12-01), Ronen
"Pentium Family User's Manual" vol. 3: Architecture and Programming Mode; Intel Corporation: 1994; primarily pp. 25-70-25-73.
John M. Mellor-Crummery and Michael L. Scott "Synchronization without Contention;" 1991 ACM 0-89791-380-9/91/0003-0269; pp. 269-278.
Maurice Herlihy "Wait-Free Synchronization" ACM Transactions on Programming Lanuages and Systems, vol. 11, No. 1, Jan. 1991, pp. 124-149.

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