Method and apparatus for the detection of reordering hazards

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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Details

395395, 395391, 39580023, 39580038, 711117, 711122, G06F 1128, G06F 1300

Patent

active

058899740

ABSTRACT:
In a computer system processing out of order commands, a method for detecting situations in which errors could be caused by execution of an out of order command. The method includes the steps of receiving a first address of a first type and receiving a next address of the first type. Information is accumulated regarding differences between the first address and the next address. The method also includes receiving an address of a second type and using the accumulated information to determine whether the address of the second type is an address associated with a command whose execution can create a hazard. A hazard indication is generated if it is determined that the address of the second type is an address associated with a command whose execution can create a hazard. In one embodiment, the first type of address is an address associated with a first type of command and the second type of address is an address associated with a second type of command. In another embodiment, the first type of command and the second type of command are the same type of command.

REFERENCES:
patent: 5471598 (1995-11-01), Quattromani et al.
patent: 5481683 (1996-01-01), Karim
patent: 5488729 (1996-01-01), Vegesna et al.
patent: 5584009 (1996-12-01), Garibay, Jr. et al.
patent: 5630149 (1997-05-01), Bluhm
patent: 5673425 (1997-09-01), Iwashita

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