Method of forming SRAM cells and pairs of field effect transisto

Details Method of forming SRAM cells and pairs of field effect transisto Method of forming SRAM cells and pairs of field effect transisto

1997-08-19

1999-11-23

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438258, 438241, 148DIG163, H01L 2100, H01L 2184

Patent

active

059899468

ABSTRACT:
A method of forming a pair of field effect transistors having different thickness gate dielectric layers includes, a) providing a first region on a substrate for formation of a first field effect transistor s having a first gate dielectric layer of a first thickness and providing a second region on the substrate for formation of a second field effect transistor having a second gate dielectric layer of a second thickness; b) providing the first gate dielectric layer and a first conductive gate layer over the first and second regions; c) patterning the first conductive layer to define a first gate of the first field effect transistor in the first region while leaving the first conductive layer not patterned for gate formation for the second field effect transistor in the second region; d) after defining the first gate, stripping the first conductive layer and the first gate dielectric layer from the second region; e) after stripping the first conductive layer and the first gate dielectric layer from the second region, providing the second gate dielectric layer and a second conductive gate layer over the second region; and f) patterning the second conductive layer in the second region to define a second gate of the second field effect transistor in the second region. The invention has particular utility in fabrication of SRAM circuitry.

REFERENCES:
patent: 4627153 (1986-12-01), Masuoka
patent: 4951112 (1990-08-01), Choi et al.
patent: 5010521 (1991-04-01), Matsui
patent: 5254489 (1993-10-01), Nakata
patent: 5285096 (1994-02-01), Ando et al.
patent: 5293336 (1994-03-01), Ishii et al.
patent: 5327002 (1994-07-01), Motoyoshi
patent: 5347152 (1994-09-01), Sundaresan
patent: 5426065 (1995-06-01), Chan et al.
patent: 5432114 (1995-07-01), O
patent: 5497021 (1996-03-01), Tada
patent: 5607868 (1997-03-01), Chida et al.
Research Disclosure, "Process to make thick and thin gate dielectric devices on the same chip", 334(2) (Feb. 1992) 117, No. 33428.
Lage, Craig et. al., "Soft Error Rate And Stored Charge Requirements in Advanced High-Density SRAMs", IEEE 1993, IEDM pp. 821-824.

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