Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1996-02-16
1998-07-07
Gossage, Glenn
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711103, 711217, 36518533, G06F 1300, G11C 1606
Patent
active
057784400
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to floating gate memory devices, such as flash erasable programmable read only memory (EPROM) or electrically erasable programmable read only memory (EEPROM), and more particularly to such devices having automatic program cycles for programming a block of data.
2. Description of Related Art
Floating gate memory devices, such as flash memory and EEPROM, provide for electrically storing data into the device. The operation of storing data has been controlled in the prior art based on commands which consist of a sequence of addresses or data, such as described in prior art U.S. Pat. No. 4,970,692, to Ali, et al.. When a particular sequence of addresses is detected, in combination with the appropriate cycling of the chip enable and write enable signals, an automatic program mode is initiated in one prior art system. The automatic program mode includes a program load cycle in which the chip receives a stream of addresses and data which are loaded into a programming data buffer. After the block of data to be programmed has been loaded into the buffer, an automatic program cycle is executed by state machines on the chip to transfer the data into the non-volatile memory array. The problem arises in detecting the end of the block of data to be stored. In prior art systems, the end of the block of data is signaled by a pulse of the chip enable or write enable signal which lasts more than 100 microseconds. The prior art devices require further that the full buffer (i.e. 256 bytes) be loaded prior to programming.
The time out sequence, based on the long 100 microsecond pulse, is time consuming and can cause problems in computer systems. For instance, interrupt signals may occur while the memory device is performing the loading of the buffer. In this case, if the interruption is longer than the 100 microsecond waiting period, then the internal state machine on the flash memory may take over and program the data in the buffer, before the entire buffer is loaded. Thus, care must be taken in systems using flash memory to prevent interrupts which take longer than 100 microseconds to service. If the duration of interrupt servicing cannot be managed, then a problem arises which cannot be addressed using prior art systems.
Accordingly, it is desirable to provide a protocol which allows for loading a block of data having an arbitrary length into a floating gate memory device, and for detecting when the end of that block has been loaded.
SUMMARY OF THE INVENTION
The present invention provides a protocol which terminates a program load cycle in an integrated circuit memory, providing positive indication of the end of the load cycle, and eliminating the requirement for a long pulse in a control signal. The invention is based on command logic which executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, and detects the last segment in a block of data in response to a pattern including at least one of the addresses and data segments received at the input/output circuitry. The command logic includes a command address/data latch, a command address/data decoder, and mode control logic. The input/output circuitry includes control input logic, an address latch and buffer, and data I/O circuitry. Thus, according to one aspect of the invention the pattern includes an address transition between consecutive matching addresses. The command logic also includes a circuit coupled to the input/output circuitry which stores addresses in the sequence and compares them with a next address to indicate a matching address. Alternatively, the pattern may include both matching addresses and data segments with corresponding comparator circuitry. Alternatively, the pattern may comprise a transition to a command address which is outside the address field of the memory array, or a transition of part of an address from a command value to a read value for the page. To terminate the program
REFERENCES:
patent: 4970692 (1990-11-01), Ali et al.
patent: 5036460 (1991-07-01), Takahira et al.
patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5109492 (1992-04-01), Noguchi et al.
patent: 5355464 (1994-10-01), Fandrich et al.
patent: 5414664 (1995-05-01), Lin et al.
patent: 5414829 (1995-05-01), Fandrich et al.
Cheng Yao-Wu
Dang-hsing Yiu Tom
Hung Chung-Hsiung
Shone Fuchia
Wan Ray-Lin
Gossage Glenn
Haynes Mark A.
Macronix International Co. Ltd.
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