Method and apparatus for interfacing a data bus to a plurality o

Details Method and apparatus for interfacing a data bus to a plurality o Method and apparatus for interfacing a data bus to a plurality o

1995-09-29

1998-07-07

Lane, Jack A.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711157, G06F 1204

Patent

active

057784124

ABSTRACT:
A method and apparatus for interfacing a data bus to a plurality of memory devices. A portion of data associated with a first address is loaded into a first cell in a first memory device. Another portion of data associated with the first address is loaded into a second cell in a second memory device. Subsequently, a portion of data associated with a second address is loaded into a third cell in the first memory device while another portion of data associated with the second address is loaded into a fourth cell in a third memory device.

REFERENCES:
patent: 4485457 (1984-11-01), Balaska et al.
patent: 4949293 (1990-08-01), Kawamura et al.
patent: 5247645 (1993-09-01), Mirza et al.
patent: 5293607 (1994-03-01), Brockmann et al.
patent: 5613094 (1997-03-01), Khan et al.

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