Lookup tables which double as shift registers

Electronic digital logic circuitry – Multifunctional or programmable – Array

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326 41, H03K 19177

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active

058894136

ABSTRACT:
A logic element for an FPGA which can be configured as any one of a random access memory, a shift register and a lookup table. The logic element includes a plurality of memory cells which are interconnected such that the data output of each cell can serve as the input to the next memory cell. Thus the logic element effectively functions as a shift register. Shift registers of arbitrary length can be created by using a lookup table address multiplexer to select any memory cell output (not necessarily the last memory cell output) of the lookup table, and by chaining lookup tables of plural logic elements in series.

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