Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

1991-05-23

1994-02-15

Mullins, James B.

Static information storage and retrieval

Read/write circuit

Data refresh

365233, G11C 700

Patent

active

052873196

ABSTRACT:
In the normal selfrefresh mode, the timer output selection circuit selects the timer output of a longer cycle from the timer outputs generated by the internal timer circuit, and the selected timer output supplied as an operation activation signal for the selfrefresh operation. Using this long timer output, the selfrefresh operation of DRAM cells in the memory device is performed with a low operating current which allows the memory device to be backed up by a battery. When the selfrefresh mode is set before the store operation, the timer output of a short cycle is selected from the timer outputs generated by the internal timer circuit, and the short timer output is supplied as an operation activation signal for the selfrefresh operation. Using this short timer output, the selfrefresh operation of the volatile memory means is performed. Therefore, a drop in the potential of the volatile memory portions caused by a leakage current can be quickly compensated, thus ensuring that data can be correctly stored in the volatile memory means. In the selfrecall operation mode, the timer output of an medium cycle is selected from the timer outputs generated by the internal timer circuit, and the medium timer output is supplied as an operation activation signal for the selfcall operation. Since the selfrecall operation is performed using the medium timer output, the selfrecall operation is performed at a faster speed than the normal selfrefresh operation.

REFERENCES:
patent: 4747082 (1988-05-01), Minato et al.
patent: 4827453 (1989-05-01), Sawada et al.
U.S. application Ser. No. 07/549,293 Filed Jul. 6, 1990.
U.S. application Ser. No. 07/308,854 Filed Feb. 9, 1989.
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U.S. application Ser. No. 07/469,346 Filed Jan. 24, 1990.
U.S. application Ser. No. 07/488,874 Filed Mar. 6, 1990.
U.S. application No. 07/481,179 Filed Feb. 20, 1990.
Terada et al., IEEE Journal of Solid-Sate Circuits Feb. (1988) 23(1):86-90.

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