Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1995-11-22
1998-07-07
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438778, 438674, H01L 21441
Patent
active
057768293
ABSTRACT:
The present invention provides a novel method for forming multilevel interconnections in a semiconductor device. A silicon oxide film is formed on a semiconductor substrate. A first photo-resist film pattern is formed on the first silicon oxide film. The surface of the silicon oxide film covered with the photo-resist film pattern is exposed to a super-saturated hydrosilicofluoric acid solution to selectively deposit a first fluoro-containing silicon oxide film on the silicon oxide film by use of the first photo-resist film pattern as a mask. The first photo-resist film pattern is removed, thereby resulting in first grooves in the fluoro-containing silicon oxide film. First interconnections are formed within the first grooves. An inter-layer insulator is formed on an entire surface of the device and then subjected to a dry etching and a photolithography to form via holes in the inter-layer insulator. Conductive films are selectively formed in the via holes. A second photo-resist film pattern is selectively formed to cover the conductive films within the via holes. The entire surface of the device covered with the second photo-resist film pattern is exposed to a super-saturated hydrosilicofluoric acid solution to selectively deposit a second fluoro-containing silicon oxide film on the inter-layer insulator by use of the second photo-resist film pattern as a mask. The second photo-resist film pattern is removed, thereby resulting in second grooves in the second fluoro-containing silicon oxide film. Second interconnections are formed within the second grooves.
REFERENCES:
patent: 5304510 (1994-04-01), Suguro et al.
patent: 5326720 (1994-07-01), Goda et al.
patent: 5328873 (1994-07-01), Mikoshiba et al.
S. Gonzales et al. "Performance of a sequentially deposited Ti/TiN/AlCuSi Metallization Structure" Proc. 1991 IEEE VLSI Multilevel Interconnect Conf. (Jun. 11-12 1991) pp. 316-319.
Homma Tetsuya
Sekine Makoto
Everhart Caridad
NEC Corporation
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