Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1992-08-25
1994-12-13
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 36523009, 36518904, 365201, G11C 700
Patent
active
053734718
ABSTRACT:
In case an address is to access a defective memory cell, a defective memory cell in a memory cell area contained in one of paired memory mats is selected in parallel with a redundant memory cell in a redundant memory cell area contained in the other memory mat. At this time of selecting the redundant main word line for selecting the redundant memory cell, there is not required the logical operation for deciding whether or not the redundant use of the access address fed from the outside is proper. For example, the redundant main word line is set to the select level on the basis of a chip select signal. As a result, the drive start timing of the redundant main word line is not delayed in the least from the drive start timing of the main word line. Thus, it is possible to prevent the event that the select drive timing of the redundant sub word line is delayed on account of the delay in the drive timing of the redundant main word line.
REFERENCES:
patent: 5021944 (1991-06-01), Sasaki et al.
patent: 5251168 (1993-10-01), Chung et al.
Abe Tadashi
Fukazawa Takeshi
Nagai Kiyoshi
Saeki Makoto
Yamamura Hisae
Hitachi , Ltd.
Hoang Huan
LaRoche Eugene R.
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