Low-RC multi-level interconnect technology for high-performance

Details Low-RC multi-level interconnect technology for high-performance Low-RC multi-level interconnect technology for high-performance

1992-03-03

1994-12-13

Thomas, Tom

Fishing, trapping, and vermin destroying

437 51, 437927, H01L 2144, H01L 2148

Patent

active

053729692

ABSTRACT:
A high-performance "low-RC" multi-level interconnect technology has been conceived for advanced sub-0.5 .mu.m semiconductor technologies. The proposed structure and fabrication process has a number of significant characteristics: (i) compatible with various metal systems (Al, Cu, W, etc.), (ii) free-space interlevel dielectrics; (iii) compatible with standard semiconductor fabrication processes, (iv) excellent mechanical stability; and (v) compatible with hermetically sealed chip packaging techniques. Compared with an Al-based conventional interconnect technology, the new interconnect system can reduce the "RC" delay by a factor of .sup.- 6. The proposed interconnect technology offers major chip performance improvements such as lower power dissipation and higher operating frequencies. This technology is based on a manufacturable process to fabricate multilevel interconnect with free-space dielectrics and a technology scaling enabler.

REFERENCES:
patent: 4918032 (1990-04-01), Jain et al.
patent: 4980034 (1990-12-01), Volfson
patent: 5000818 (1991-03-01), Thomas et al.

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