Memory cell with improved single event upset rate reduction circ

Details Memory cell with improved single event upset rate reduction circ Memory cell with improved single event upset rate reduction circ

1988-09-30

1990-09-11

Moffitt, James W.

Static information storage and retrieval

Systems using particular element

Flip-flop

G11C 1140

Patent

active

049568140

ABSTRACT:
The rate of single event upset in a memory cell due to energetic particle hits on a p-channel device is reduced by a pair of active devices in the cross-coupling between a pair of inverters. The active devices are controlled by voltages internal to the memory cell such that writing into the cell is not slowed significantly. Additionally, means such as a resistor or transistor are disclosed which reduce the rate of single event upset due to energetic particle hits on a n-channel device.

REFERENCES:
patent: 4387444 (1983-06-01), Edwards
patent: 4725981 (1988-02-01), Rutledge
patent: 4779226 (1988-10-01), Haraszti
"CMOS RAM Cosmic Ray-Induced Error Rate Analysis", J. C. Pickel, et. al., IEEE Trans. on Nuclear Science, vol. NS-28, pp. 3962-3967 (1981).

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