Boots – shoes – and leggings
Patent
1996-09-25
1998-08-04
Teska, Kevin J.
Boots, shoes, and leggings
364489, 364490, 25049222, G06F 1750, H01L 23528
Patent
active
057904170
ABSTRACT:
A method is provided for producing a dummy pattern for an I.C. semiconductor device multi-layer interconnection metallurgy, having a planar global top surface with a dummy pattern for a circuit for use with conductor lines in the circuit pattern. Create a reverse pattern which is a complement of a widened conductor lines in the circuit pattern with openings about the location of the circuit pattern and provide a dummy cross grid pattern. A gridded dummy pattern is generated by creating a dummy grid pattern of the reverse pattern combining it with the negative of the dummy cross grid pattern leaving a cross grid of dummy elements and openings about the location of the circuit pattern. Provide a revised pattern by adding the circuit pattern to the gridded dummy pattern. Take the product of a contact layout pattern multiplied times the sizing operator multiplied times a separation parameter. Then subtract the sized and separated contact layout pattern from the gridded dummy pattern. Then multiply the dummy pattern times a function of sizing operators, and provide a revised contact and circuit pattern by adding the circuit pattern to the sized dummy pattern.
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Chao Ying-Chen
Chen Chia-Hsiang
Sheu Jhy-Sheng
Ackerman Stephen B.
Do Thuan
Jones II Graham S.
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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