Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Patent
1998-09-25
2000-04-11
Auve, Glenn A.
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
713500, G06F 1300
Patent
active
060498463
ABSTRACT:
A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device includes clock receiver circuitry, clock generation circuitry and input receiver circuitry. The clock receiver circuitry receives an external clock signal from an external bus. The clock generation circuitry is coupled to the clock receiver circuitry, and includes a delay locked loop to generate a first internal clock signal. The input receiver circuitry is coupled to the clock generation circuitry and the external bus to sample information from the external bus in response to the first internal clock signal.
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Farmwald Michael
Horowitz Mark
Auve Glenn A.
Rambus Inc.
Steinberg Neil A.
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