Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1996-12-20
1999-10-05
Gossage, Glenn
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711 5, 36518511, 36518533, 36518529, 365236, G06F 1300, G06F 1216, G11C 1602
Patent
active
059639709
ABSTRACT:
A method and apparatus for keeping track of erase cycles performed on a plurality of storage blocks in a flash memory device. The flash memory device comprises at least two wear-bar blocks (active and inactive) for use in storing a plurality of erase count values representing the erase cycles performed on the plurality of storage blocks. Each wear-bar block includes a plurality of wear-bar storage elements corresponding to each of the plurality of storage blocks. Each wear-bar storage element includes a first count field and a second count field which collectively contain an erase count value. The second count field may be updated by changing from an initial state (SET, e.g.) to a final state (CLEAR, e,g.) without erasure of its corresponding wear-bar block. The first count field is updated in a normal binary sequence each time the second count field reaches a maximum count (e.g., all bits are changed from SET to CLEAR). When that occurs, the contents of the active wear-bar block are transferred to the inactive wear-bar block, the active wear-block is completely erased becoming the inactive wear-bar block, while the previously inactive wear-bar block becomes the active wear-bar block. In this manner, the wear bar blocks will not be worn out before the storage blocks and can be used as a reliable indicator of the number of erase cycles for the storage blocks.
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patent: 4922456 (1990-05-01), Naddor et al.
patent: 5268870 (1993-12-01), Harari
patent: 5341339 (1994-08-01), Wells
patent: 5485595 (1996-01-01), Assar et al.
patent: 5544356 (1996-08-01), Robinson et al.
Gossage Glenn
Intel Corporation
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