Series MOS ROM with tapered oxide side walls

Details Series MOS ROM with tapered oxide side walls Series MOS ROM with tapered oxide side walls

1996-04-23

1996-12-24

Larkins, William D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257900, 365104, H01L 27112

Patent

active

055876005

ABSTRACT:
A read-only-memory having a plurality of very narrow, closely spaced gate electrodes spanning the distance between source and drain regions. The gate electrodes consist of first and second alternating polycrystalline silicon lines having vertical sidewalls. The first lines have tapered sidewall spacers. The second lines are entirely contained between the first lines without overlap of the first lines.

REFERENCES:
patent: 4775550 (1988-10-01), Chu et al.
patent: 4826786 (1989-05-01), Merenda et al.
patent: 4894351 (1990-01-01), Batty
patent: 4986878 (1991-01-01), Malazgirt et al.
patent: 5002896 (1991-03-01), Naruke
patent: 5149667 (1992-09-01), Choi

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