Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-03-10
1998-08-04
Niebling, John
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438639, H01L 214763
Patent
active
057893160
ABSTRACT:
A method for forming a narrow via through a portion of an integrated circuit layer between a pair of integrated circuit structures within an integrated circuit. There is first provided a substrate layer having a pair of integrated circuit structures formed thereupon. The integrated circuit structures are separated by a width over the substrate layer no less than the width of a narrow via desired to be formed through a portion of a first integrated circuit layer formed between the pair of integrated circuit structures plus two times a registration tolerance of a photoexposure apparatus employed in defining the location of a wide via from which is formed the narrow via plus two times a minimum integrated circuit layer width separating the narrow via from each integrated circuit structure within the pair of integrated circuit structures. There is then formed over the substrate layer and upon the integrated circuit structures the first integrated circuit layer. There is then formed through the portion of the first integrated circuit layer between the integrated circuit structures a wide via of width equal to the width of the narrow via plus two times the minimum integrated circuit layer width separating the narrow via from each integrated circuit structure. There is then formed conformally into the wide via a conformal second integrated circuit layer of thickness substantially equal to the minimum integrated circuit layer width separating the narrow via from each integrated circuit structure. There is then anisotropically etched the conformal second integrated circuit layer to remove completely a central portion of the conformal second integrated circuit layer at the bottom of the wide via while not substantially etching the portions of the conformal second integrated circuit layer formed upon the sidewalls of the wide via.
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Ackerman Stephen B.
Lebentritt Michael S.
Niebling John
Saile George O.
Szecsy Alek P.
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