Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-07-17
1998-08-04
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438637, 438660, 257760, H01L 21441
Patent
active
057893152
ABSTRACT:
An improved integrated circuit manufacturing process for forming interlevel dielectrics in multilevel metallization structures eliminates extrusions of metal into vias following via etch. The deposition temperature of the conformal dielectric liner is controlled relative to the subsequent degas temperature, thereby lowering thermal compressive stresses in the metal layer.
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Bruce L. Draper, et al. "Stress and Stress Relaxation in Integrated Circuit Metals and Dielectrics" J. Vac. Sci. Technol. B 9(4) pp. 1956-1961, Jul./Aug. 1991.
Arthur T. Learn, "Suppression of Aluminum Hillock Growth . . . " J. Vac. Sci. Tech. B 4(3) May/Jun. 1986 pp. 774-776.
H. Shibata et al, "Via hole-related simultaneous stress-induced Extrusion and Void Formation in Al interconnects," 1993 IEEE IRPS Proc., pp. 340-344 (1993).
Besser Paul R.
Cheung Robin W.
Advanced Micro Devices , Inc.
Everhart Caridad
Fisher Gerald M.
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