Eliminating metal extrusions by controlling the liner deposition

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438637, 438660, 257760, H01L 21441

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active

057893152

ABSTRACT:
An improved integrated circuit manufacturing process for forming interlevel dielectrics in multilevel metallization structures eliminates extrusions of metal into vias following via etch. The deposition temperature of the conformal dielectric liner is controlled relative to the subsequent degas temperature, thereby lowering thermal compressive stresses in the metal layer.

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patent: 5405805 (1995-04-01), Homma
patent: 5453402 (1995-09-01), Cheung et al.
patent: 5457073 (1995-10-01), Ouellet
Bruce L. Draper, et al. "Stress and Stress Relaxation in Integrated Circuit Metals and Dielectrics" J. Vac. Sci. Technol. B 9(4) pp. 1956-1961, Jul./Aug. 1991.
Arthur T. Learn, "Suppression of Aluminum Hillock Growth . . . " J. Vac. Sci. Tech. B 4(3) May/Jun. 1986 pp. 774-776.
H. Shibata et al, "Via hole-related simultaneous stress-induced Extrusion and Void Formation in Al interconnects," 1993 IEEE IRPS Proc., pp. 340-344 (1993).

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