Semiconductor CMOS device with circuit for preventing latch-up

Details Semiconductor CMOS device with circuit for preventing latch-up Semiconductor CMOS device with circuit for preventing latch-up

1997-08-20

1999-10-05

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257173, 257174, 257328, 257355, 257356, 257357, 257358, 257359, 257360, H02H 320

Patent

active

059629029

ABSTRACT:
A semiconductor device has a substrate bias generating circuit for generating a substrate bias to be applied to a p-type semiconductor substrate, a CMOS circuit formed on the semiconductor substrate, and a latch-up protection circuit. The latch-up protection circuit has an n-type first region, a highly doped n-type second region, a p-type third region apart from the second region, in the first region and an n-type fourth region surrounding said first region formed apart from the first region on the surface of the substrate. The second region is coupled with a power supply Vcc, the third region is coupled with an input line, the fourth region is coupled with a ground Vss, and the substrate is coupled with the substrate bias generating circuit.

REFERENCES:
patent: 4476476 (1984-10-01), Yu et al.
patent: 4647956 (1987-03-01), Shrivastava et al.
patent: 4686602 (1987-08-01), Bucksch
patent: 4870530 (1989-09-01), Hurst et al.
patent: 5468984 (1995-11-01), Efland et al.
patent: 5629544 (1997-05-01), Voldman et al.

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