Multi-chip interconnection package

Details Multi-chip interconnection package Multi-chip interconnection package

1988-12-15

1990-02-13

James, Andrew J.

357 54, 357 55, 357 70, 357 73, 357 74, 357 80, H01L 2316, H01L 2348, H01L 2302

Patent

active

049011367

ABSTRACT:
A package for interconnecting a plurality of integrated circuit chips into a functional unit comprising a multilayer substrate having ground and power conducting layers and a frame for holding the chips with their terminal pads on the side of the frame opposite the substrate. Power and ground terminal pads on the chips are coupled to the appropriate potentials via registering conductive feedthroughs passing through the frame and into the substrate into contact with appropriate power or conductive layers in the substrate. Signal pads on the chips are interconnected by means of a conductive layer which is located over the chips on the side of the frame opposite the substrate.

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Archey et al., "Integrated Magnetic Memory Structure", IBM Technical Disclosure Bulletin, vol. 14, No. 7, Dec. 1971.

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