Method and apparatus for optimizing ECC memory performance

Details Method and apparatus for optimizing ECC memory performance Method and apparatus for optimizing ECC memory performance

1997-03-03

1999-10-05

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714800, 714752, G06F 1110, H03M 1312

Patent

active

059616601

ABSTRACT:
A method and apparatus for providing a memory system having error checking and correction (ECC) capability, and parity error detection capability on the same memory card, and user selection of either capability using the same type of memory modules. A memory controller having programmable configuration registers is provide for user selection of either ECC or parity capability. Eight-byte Dual in-line Memory Modules are used to provide 64-bit data which allows the memory controller to use eight extra bits for both ECC and parity capability.

REFERENCES:
patent: 5313475 (1994-05-01), Cromer et al.
patent: 5488691 (1996-01-01), Fuoco et al.

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