Power consumption reduced register circuit

Details Power consumption reduced register circuit Power consumption reduced register circuit

1998-07-27

2000-08-08

Sheikh, Ayaz R.

Electrical computers and digital processing systems: support

Computer power control

Power conservation

713601, 377 77, G06F 132, H03K 301

Patent

active

061016098

ABSTRACT:
The present invention provides a power consumption reduced register circuit which performs data processing in low power consuming and no wasteful manner. Reduction in power consumption of a synchronous circuit for accepting and outputting of data in synchronization with clock signals is achieved. An input to and output from a register are monitored and compared for outputting a determination result signal. A logical sum of an input determination control signal and the determination result signal is obtained in an OR gate, the output of which is latched to a D type flip-flop in synchronization with an invented signal of a clock signal input to the register. A logical product of the output of the flip-flop and the clock signal is obtained by an AND gate, the output signal from which is applied to the register as a clock signal.

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