System for multisized bus coupling in a packet-switched computer

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

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710129, 710132, 710 38, 710 66, G06F 1300

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active

061015652

ABSTRACT:
A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width. In an alternative embodiment, the data transfer control system transfers the data words at substantially the full rate available, given the computer system's processor or clock speed and the width of the master bus, and the words are buffered before transference to the second bus. The speed of transference to the buffer is then not limited by the size of the second bus, but only by the size of the buffer, which preferably has an input bus at least as wide as that of the master bus. The system accommodates functional units of different sizes all to be couple to a master bus of a given size, where the different sizes may be larger or smaller than the master bus size, and accordingly the functional units can be built with optimal bus sizes for their particular functions without having to conform to a perhaps inappropriate, inefficient or expensive or wasteful master bus size.

REFERENCES:
patent: 4228503 (1980-10-01), Waite
patent: 4309754 (1982-01-01), Dinwiddie, Jr.
patent: 4683534 (1987-07-01), Tietjen et al.
patent: 4716527 (1987-12-01), Graciotti
patent: 4860198 (1989-08-01), Takenaka
patent: 4949246 (1990-08-01), O'Dell et al.
patent: 5036459 (1991-07-01), Petrus den Haan
patent: 5043935 (1991-08-01), Taniai et al.
patent: 5113369 (1992-05-01), Kinoshita
patent: 5165037 (1992-11-01), Culley
patent: 5220651 (1993-06-01), Larson
patent: 5319753 (1994-06-01), MacKenna
patent: 5388227 (1995-02-01), McFarland
patent: 5394528 (1995-02-01), Kobayashi et al.
patent: 5423009 (1995-06-01), Zhu
patent: 5428763 (1995-06-01), Lawler
patent: 5428799 (1995-06-01), Woods
patent: 5430849 (1995-07-01), Banks
patent: 5454084 (1995-09-01), Uchikoga
patent: 5471632 (1995-11-01), Gavin et al.
patent: 5509126 (1996-04-01), Oprescu et al.
patent: 5526495 (1996-06-01), Shibata et al.
patent: 5537624 (1996-07-01), Whitesell
patent: 5537659 (1996-07-01), Nakao
patent: 5548766 (1996-08-01), Kaneko et al.
patent: 5548786 (1996-08-01), Amini et al.
patent: 5553244 (1996-09-01), Norcross et al.
patent: 5559969 (1996-09-01), Jennings
patent: 5590287 (1996-12-01), Zeller et al.
patent: 5594877 (1997-01-01), Lentz et al.
patent: 5630099 (1997-05-01), MacDonald et al.
patent: 5664122 (1997-09-01), Rabe et al.
patent: 5689659 (1997-11-01), Tietjen et al.
patent: 5761456 (1998-06-01), Titus et al.
patent: 5768546 (1998-06-01), Kwon
patent: 5781918 (1998-07-01), Lieberman et al.
patent: 5911053 (1999-06-01), Pawlowski et al.
"The SPARC Architecture Manual", Version 9, SPARC International, Inc., Menlo Park, California; 1994; "8 Memory Models"; pp. 117-129 & 256-262.
D. Alpert, et al., "Architecture of the NS32532 Microprocessor", Proceeding/IEEE International Conference on Computer Design: VLSI in Computers & Processors, IEEE Computer Society Press, Oct. 5, 1987, pp. 168-172.
Jung-Herng Chang, et al., "A Second-Level Cache Controller for a Super-Scalar Sparc Processor", Spring Sompcon 92, IEEE Computer Society Press, Feb. 24, 1992, pp. 142-151.
K. Lantz, et al., "Rochester's Intelligent Gateway", Computer, vol. 15, No. 10 (Oct. 1982), pp. 54-68.
M. Cvijovic, et al., "An Approach to the Design of Distributed Real-Time Operating Systems", Microprocessors and Microsystems, vol. 16, No. 2, 1992, pp 81-89.

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