Static random access memory device with memory cell testing circ

Static information storage and retrieval – Read/write circuit – Testing

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36518907, 371 211, G11C 700

Patent

active

054002818

ABSTRACT:
A static random access memory device in which a time required for testing memory cells Is shortened. The static random access memory device includes a test mode setting circuit for activating, in a test mode, a plurality of write circuits and a plurality of sense amplifiers. The device also includes a test mode switching circuit. An input data from an input circuit is written in the plurality of memory cells simultaneously through the write circuits. A plurality of data read out from the memory cells simultaneously are transferred to the test mode switching circuit which decides coincidence among the read data. On the basis of the decision result, an output circuit outputs at a data output terminal output signals in three states, that is, in a logic "1", a logic "0" or a high impedance. Since the plurality of memory cells are checked simultaneously, the required time for testing the memory cells can be shortened.

REFERENCES:
patent: 4860295 (1989-08-01), Tobita
patent: 4873669 (1989-10-01), Furutani et al.

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