Semiconductor chip packaging having printed circuitry or printed

Details Semiconductor chip packaging having printed circuitry or printed Semiconductor chip packaging having printed circuitry or printed

Filed on

1994-10-21

Date issued

2000-08-08

Examiner

Clark, Sheila V.

Patent Class

Active solid-state devices (e.g., transistors, solid-state diode

SubClass

Housing or package

SubSubClass

With contact or lead

Other Related Categories

257700, 257724, H01L 2348, H01L 2352

Type

Patent

Status

active

Patent number

061005819

Description

ABSTRACT:
A semiconductor device comprising at least one semiconductor chip, the or each semiconductor chip having a plurality of chip bonding pads, a package which encloses the at least one semiconductor chip, a first level interconnect comprising a printed circuit which overlies the at least one semiconductor chip in the package and extends externally of the package to provide a plurality of outer leads, and a second level interconnect comprising means for electrically connecting the chip bonding pads to selected contacts on the printed circuit, which contacts overlie the at least one semiconductor chip. The invention also relates to a method of manufacturing such a semiconductor device and to a method of assembling a semiconductor assembly.

REFERENCES:
patent: 4751482 (1988-06-01), Fukuta et al.
patent: 4868638 (1989-09-01), Hirata et al.
patent: 4890152 (1989-12-01), Hirata et al.
patent: 4890153 (1989-12-01), Wu
patent: 4903120 (1990-02-01), Beene et al.
patent: 4914741 (1990-04-01), Brown et al.
patent: 4941033 (1990-07-01), Kishida et al.
patent: 4953005 (1990-08-01), Carlson et al.
patent: 5018005 (1991-05-01), Lin et al.
patent: 5045921 (1991-09-01), Lin et al.
patent: 5073816 (1991-12-01), Wakefield et al.

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