Forming a self-aligned silicide gate conductor to a greater thic

Details Forming a self-aligned silicide gate conductor to a greater thic Forming a self-aligned silicide gate conductor to a greater thic

1998-07-15

2000-08-08

Nelms, David

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438555, 438581, 438582, H01L 213205

Patent

active

061001732

ABSTRACT:
An integrated circuit fabrication process is provided for using a dual salicidation process to form a silicide gate conductor to a greater thickness than silicide structures formed upon source and drain regions of a transistor. A high K gate dielectric residing between the gate conductor and the substrate substantially inhibits consumption of the junctions during the formation of the silicide gate conductor. In an embodiment, a relatively thick layer of refractory metal is deposited across a transistor arranged upon and within a silicon-based substrate. The transistor includes a polysilicon gate conductor arranged upon a portion of a high K gate dielectric interposed between a pair of source and drain junctions. The refractory metal is heated to convert the polysilicon gate conductor to a silicide gate conductor. After removing the gate dielectric from the source and drain regions, a relatively thin layer of refractory metal is deposited across the topography and heated to form silicide structures upon the source and drain regions.

REFERENCES:
patent: 5496750 (1996-03-01), Moslehi
patent: 5604138 (1997-02-01), Lee et al.
patent: 5739573 (1998-04-01), Kawaguchi
patent: 5798278 (1998-08-01), Chan et al.

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