System for designing and manufacturing CMOS inverters by estimat

Details System for designing and manufacturing CMOS inverters by estimat System for designing and manufacturing CMOS inverters by estimat

1998-03-02

2000-08-08

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 2, 326104, 326108, 326121, G06F 1750

Patent

active

060995769

ABSTRACT:
A system for simplifying and expediting estimation of the gate RC delay and/or the determination of transistor widths for a given gate RC delay in a CMOS inverter circuit. The system determines gate RC delay as a function of transistor width. Alternatively, appropriate transistor widths may be determined based on a desired optimum gate RC delay. An analytical expression is established to predict RC induced gate propagation delay as a function of readily available technical parameters in the early stage of design. The analytical expression has been found to describe gate RC delay in CMOS inverter circuits incorporating 0.25 micron (or even smaller) manufacturing technology.

REFERENCES:
Takagi et al "A Novel 0.15 uM CMOS Technolgy Using W/WNx/Polysilicon Gate Electrode And Ti Silicided Source/Drain Diffusions," IEEE, pp. 17.6.1-17.6.4, 1996.
Taur et al "CMOS Devices Below 0.1 uM: How High Will Performance Go? " IEEE, pp. 9.1.1-9.1.4, Dec. 1997.
Lai et al "Design And Implementation Of Differential Cascode Voltage Switch With Pass-Gate (DCVSPG) Logic For High-Performance Digital Systems," IEEE, pp. 563-573, Apr. 1997.

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