Electrically erasable programmable non-volatile semiconductor me

Details Electrically erasable programmable non-volatile semiconductor me Electrically erasable programmable non-volatile semiconductor me

1994-12-20

1996-12-31

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257326, 36518517, H01L 29788

Patent

active

055896995

ABSTRACT:
The structure of the invention employs a lamination type memory cell and a lamination type select transistor having a floating gate. Since no contact holes are formed in a first polysilicon film of a high resistance, it is not necessary to form a contact hole in the gate wire of the select transistor between a cell array. A floating gate is beforehand charged with electricity so that the select transistor cab have a positive threshold value. Alternatively, an impurity is introduced into the channel region of the select transistor so that the neutral threshold voltage of the transistor after radiation of ultraviolet rays can have a positive value.

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Aritome et al., "A 1.13.mu.m.sup.2 Memory Cell Technology for Reliable 3.3V 64M NAND EEPROMs", International Conference on Solid State Devices and Materials, 29 Aug. 1993, pp. 446-448.
Adler, Densely Arrayed EEPROM Having Low-Voltage Tunnel Write, IBM.RTM. Technical Disclosure Bulletin, vol. 27, No. 6, Nov. 1984.

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