Self-aligned buried channel/junction stacked gate flash memory c

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257322, H01L 2978

Patent

active

054689813

ABSTRACT:
An improved one-transistor flash EEPROM cell structure and a method for making the same is provided so that the effective channel length dimension is independent of the critical dimensions of the stacked gate structure. The cell structure (110) includes an n.sup.- buried channel/junction region (116) which is implanted in a substrate (112) before formation of a tunnel oxide (126) and a stacked gate structure (134). After the formation of the stacked gate structure, a p-type source region (122) is implanted with a large tilt angle in the substrate. Thereafter, n.sup.+ drain and n.sup.+ source regions (118, 124) are implanted in the substrate so as to be self-aligned to the stacked gate structure. The cell structure of the present invention facilitates scalability to small size and is useful in high density and low voltage power supply applications.

REFERENCES:
patent: 4161039 (1979-07-01), Rossler
patent: 5147811 (1992-09-01), Sakagami
patent: 5278787 (1994-01-01), Iwasa
patent: 5349220 (1994-09-01), Hong
patent: 5378909 (1995-01-01), Chang et al.

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