Network interface circuit including an address translation unit

Details Network interface circuit including an address translation unit Network interface circuit including an address translation unit

1996-07-01

1999-08-10

Gossage, Glenn

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711108, 711135, 711203, 711210, G06F 1210, G11C 1500

Patent

active

059374365

ABSTRACT:
A network interface circuit including an address translation unit and a flush check circuit, and a method for checking for an invalid address translation within of the address translation unit, are disclosed. A flush check circuit, in communication with the address translation unit, is implemented to determine, prior to loading an address translation into the internal memory, whether one of the plurality of entries already contains a virtual address utilized by the address translation. If so, an error has occurred with the flushing operations of the address translation unit because the address translation should have already been removed. In response, the flush check circuit signals logic to perform error handling techniques such as issuing an error signal, storing the invalid address translation unit, or transmitting the virtual address of the address translation without loading that address translation. The memory of the address translation unit may include a content addressable memory (CAM) element configured to contain the virtual page number of an address translation, and a random access memory (RAM) element configured to contain a physical page number of that address translation. In one embodiment, the flush check circuit may include flush management logic to detect whether a flush check mode is enabled via a control register.

REFERENCES:
patent: 4488256 (1984-12-01), Zolnowski et al.
patent: 5606683 (1997-02-01), Riordan
patent: 5675763 (1997-10-01), Mogul
patent: 5682495 (1997-10-01), Beavers et al.
patent: 5784709 (1998-07-01), McLellan et al.
"Testability Features of the MC68851 PMMU", Giles et al., Proceedings of the Interntional Test Conference 1986, Sep. 8, 1986, Washington, p.408-411 .

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