Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-07-14
1999-08-10
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438622, 438623, 438626, 438761, 438780, 438787, 438790, 438329, 438253, 438256, 438257, 438396, H01L 27108
Patent
active
059373229
ABSTRACT:
A silicon oxide film is formed on a wire array by CVD employing a gas mixture composed of a gas containing silicon atoms and hydrogen peroxide, and the thickness of the silicon oxide film in the region apart from the wire array is formed to be at least 50% of the wire thickness. Planarization of the silicon oxide film over the wire array region is attained.
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Technical Digest of IEDM '94, Novel Self-planarizing CVD Oxide for Interlayer Dielectric Applications M.Matsuura, et al, (4 pages).
Proceedings of DUMIC '95, "Planarization for Sub-micron Device utilising a New Chemistry" A. Kiemasz, et al pp. 94-100.
A. Kiermasz, et al., 1995 DUMIC Conference, pp. 94-100, Feb. 21 and 22, 1995, "Planarisation for Sub-Micron Devices Utilising a New Chemistry".
Bowers Charles
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Thanh
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