MOS transistor with impurity-implanted region

Details MOS transistor with impurity-implanted region MOS transistor with impurity-implanted region

1996-10-22

1999-08-10

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257345, 257408, 438163, 438179, 438286, 438305, 438306, 438307, H01L 27088

Patent

active

059362774

ABSTRACT:
A MOS transistor includes a semiconductor substrate of a first conductivity type having a major surface, a source and drain of a second conductivity type formed on the major surface to define a channel region therebetween, and a gate arranged in the channel region via an insulating film. The MOS transistor includes an impurity-implanted region of the first conductivity type located at a substrate portion which is deeper than the channel region and is shifted to a source side from a region corresponding to the channel region.

REFERENCES:
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patent: 5448101 (1995-09-01), Ono et al.
patent: 5512770 (1996-04-01), Hong
patent: 5536959 (1996-07-01), Kellam
patent: 5545572 (1996-08-01), Lee et al.
patent: 5552623 (1996-09-01), Nishizawa et al.
A. Hiroki et al; "A High Performance 0.1 .mu.m MOSFET with Asymmetric Channel Profile"; 1995, pp. 17.7.1-17.7.4; IEDM 95-439.
H. Hwang et al; "Performance and Reliability Optimization of Ultra Short Channel CMOS Device for Giga-bit DRAM Applications"; 1995; pp. 17.6.1-17.6.4, IEDM 95-435.
T. Hori; "A 0.1 .mu.m CMOS Technology with Tilt-Implanted Punchthrough Stopper (TIPS)";1994; pp. 4.3.1-4.3.4, IEDM 94-75.
S. Shimizu et al; "0.1.mu.m CMOS Process for High Performance and High Reliability" 1994; pp. 4.1.1-4.1.4; IEDM 94-67.
A. Hori et al; 0.05.mu.m-CMOS with Ultra Shallow Source/Drain Junctions Fabricated by 5KE V Ion Implantation and Rapid Thermal Annealing; 1994; pp. 19.1.1-19.1.4; IEDM 94-485.

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