Stacked CMOS latch with cross-coupled capacitors

Details Stacked CMOS latch with cross-coupled capacitors Stacked CMOS latch with cross-coupled capacitors

1993-11-23

1994-09-13

Nguyen, Viet Q.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257305, 257296, 257300, 365182, H01L 2710, G11C 1134

Patent

active

053471520

ABSTRACT:
A latch (80) utilizing stacked MOS technology is provided. Latch (80) is formed generally in relation to a semiconductor substrate (82). An N channel transistor is provided with first and second diffused regions (96 98) and a gate conductor (86) . A P channel transistor is provided with first and second doped regions (106, 110) having a channel region (108) therebetween. The second diffused region (98) of the N channel transistor also functions as the gate conductor for the P channel transistor. A capacitive element exists by having an insulating layer (84) or layers (84, 100) between first doped region (104) and second diffused region (98).

REFERENCES:
patent: 4622571 (1986-11-01), Hara
patent: 4654121 (1987-03-01), Miller et al.
patent: 4771323 (1988-09-01), Sasaki
patent: 4839707 (1989-06-01), Shields
patent: 4849801 (1989-07-01), Honjyo et al.
patent: 4888631 (1989-12-01), Azuma et al.
patent: 4901124 (1990-02-01), Seki
patent: 4924278 (1990-05-01), Logie
patent: 5016070 (1991-05-01), Sundaresan

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