Synchronous semiconductor memory device

Details Synchronous semiconductor memory device Synchronous semiconductor memory device

1997-07-25

1998-08-18

Mai, Son

Static information storage and retrieval

Read/write circuit

Data refresh

36523003, 365233, G11C 700

Patent

active

057966699

ABSTRACT:
Switches (11, 12) select either of refresh address counters (6a, 6b) in accordance with a refresh bank set signal (.phi.REFADD) when a bank refresh signal (.phi.BANKREF) is activated. An internal bank address (int.BA) serves as the refresh bank set signal (.phi.REFADD) to control the switch (12) and the refresh address counter (6a or 6b) designated by the internal bank address (int.BA) performs a count operation in synchronization with a refresh clock (.phi.REFCLK). The switch (11) outputs either of refresh addresses (Ref.Add.sub.-- A<0:10>, Ref.Add.sub.-- B<0:10>) which is updated. With this configuration provided is an SDRAM which allows access to data during a refresh operation.

REFERENCES:
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5535169 (1996-07-01), Endo et al.
patent: 5598372 (1997-01-01), Matsumoto et al.

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