Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1997-07-28
1998-08-18
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257347, 257503, 365149, 438253, H01L 2348
Patent
active
057961670
ABSTRACT:
An insulation layer is formed on a silicon substrate. An SOI layer is formed on the insulation layer. A groove is selectively formed in the insulation layer. A bit line is buried in a lower half of the groove. A connection conductor layer is selectively formed on the side wall surface of the groove on the buried bit line. The SOI layer and the buried bit line are connected electrically via the connection conductor layer. A cap insulation layer is formed to fill the groove on the buried bit line in a region where said connection conductor layer is not formed.
REFERENCES:
patent: 5414285 (1995-05-01), Nishihara
patent: 5596230 (1997-01-01), Hong
patent: 5670812 (1997-09-01), Adler et al.
patent: 5702969 (1997-12-01), Lee
Y. Kohyama, et al., "Buried Bit-Line Cell for 64MB DRAMs," 1990 Symposium on VLSI Technology, Digest of Technical Papers, 1990; pp. 17-18.
Crane Sara W.
NEC Corporation
Wille Douglas A.
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