Semiconductor memory using different concentration impurity diff

Details Semiconductor memory using different concentration impurity diff Semiconductor memory using different concentration impurity diff

1995-09-08

1998-08-18

Monin, Donald

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257401, 257408, 365104, H01L 2976, H01L 2994

Patent

active

057961492

ABSTRACT:
A semiconductor memory which includes first and second memory cells, wherein the first memory cells include first MOS transistors each having impurity diffused layers provided inside of both of a source and a drain to expanding source and drain regions, the second memory cells include second or third MOS transistors each having an impurity diffused layer provided inside of one of a source and a drain or include fourth MOS transistors each having no impurity diffused layer provided inside of either thereof, as well as a method for fabricating the semiconductor memory. Differences in threshold voltage between the first and second to fourth MOS transistors are utilized as differences in storage status between the first and second memory cells so that data "0" or "1" is stored in each memory cell. There are also provided a semiconductor memory wherein differences between the first to fourth MOS transistors in the drain-source current flowing through the transistors when subjected to application of an identical gate voltage thereto are utilized to store four sorts of data in one memory cell, and provided a method for fabricating the semiconductor memory.

REFERENCES:
patent: 4467520 (1984-08-01), Shiotari
patent: 4837181 (1989-06-01), Galbiati et al.
patent: 5592012 (1997-01-01), Kubota
IEEE Transactions on Computers, vol. C-35, No. 2, Feb. 1986, A Survey of Multivalued Memories.

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