DRAM semiconductor device with composite bit line

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257310, H01L 27108

Patent

active

057961360

ABSTRACT:
N.sup.+ impurity diffusion layers, and a gate electrode are formed on a major surface of a p-type semiconductor substrate. An insulating layer, and interlayer insulating layers are formed to cover gate electrode. An interconnection layer provided with a hole is formed on interlayer insulating layer. A contact hole is provided in interlayer insulating layer and a column-like portion is formed within the contact hole and hole. The column-like portion and interconnection layer constitute a bit line. Thus, the resistance of the bit line can be reduced and the manufacturing process of the device can be simplified.

REFERENCES:
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patent: 5158905 (1992-10-01), Ahn
patent: 5242852 (1993-09-01), Matsuyama et al.
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patent: 5539231 (1996-07-01), Suganaga et al.
patent: 5561311 (1996-10-01), Hamamoto et al.
patent: 5583358 (1996-12-01), Kimura et al.
Jeffrey Marks et al, "Etching Using High Density Plasma", pp. 68-75, Semiconductor World 1993, no month.

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